The present invention relates to a method of producing a semiconductor memory. More specifically, the present invention relates to a method of producing a semiconductor memory, in which each of a plurality of memory cell transistors formed on a semiconductor substrate includes a laminated gate formed of a floating gate and a control gate.
A non-volatile semiconductor memory has a property of holding data stored therein even after power is turned off, and has been used for storing firmware or supplying application though a cartridge.
An EPROM (Erasable Programmable Read-Only Memory) is one type of the non-volatile semiconductor memory. A plurality of memory cell transistors constitutes the EPROM, and each of the memory cell transistors includes a laminated gate (a double gate) formed of a floating gate and a control gate.
When data are written into the EPROM, a source and a substrate are grounded, and a high voltage is applied to a drain and the control gate. As a result, electrons moving in a channel from the source to the drain capture high kinetic energy and become hot electrons. Some of the hot electrons jump over a gate oxide film and pour into the floating gate. Accordingly, data of one bit are written in the memory cell transistor.
In this case, the floating gate has a negative potential due to negative electrons pouring into the floating gate. As a result, a threshold voltage Vth1 of the memory cell transistor relative to the control gate becomes greater than an initial value Vth0. Accordingly, when data are read out, a voltage between the threshold voltage Vth1 and the initial value Vth0 is applied to the control gate, and it is determined that a value of the memory cell transistor is “0” or “1” depending on whether the memory cell transistor is turned on or not. In the EPROM, a large number of the memory cell transistors described above are arranged on a semiconductor substrate, thereby constituting a large capacity memory device.
FIGS. 1(a) to 1(e) are views showing a method of producing a conventional non-volatile semiconductor memory having a laminated gate structure. More specifically, FIGS. 1(d) and 1(e) are plan views of the conventional non-volatile semiconductor memory; FIG. 1(a) is a sectional view taken along a line 1a-1a in FIG. 1(d); FIG. 1(b) is a sectional view taken along a line 1b-1b in FIG. 1(e); and FIG. 1(c) is a sectional view of the conventional non-volatile semiconductor memory.
FIGS. 2(a) to 2(e) are views showing the method of producing the conventional non-volatile semiconductor memory having a laminated gate structure. More specifically, FIGS. 2(d) and 2(e) are plan views of the conventional non-volatile semiconductor memory; FIG. 2(a) is a sectional view taken along a line 2a-2a in FIG. 2(d); FIG. 2(b) is a sectional view of the conventional non-volatile semiconductor memory; and FIG. 2(c) is a sectional view taken along a line 2c-2c in FIG. 2(e).
As shown in FIGS. 1(a) and 1(d), first, a silicon (Si) single crystal substrate 1 (a substrate 1) is prepared. Then, element separation regions 20 are formed in the substrate 1 for separating an active region through a well-known element separation technology. Then, an impurity is implanted into the active region of the substrate 1 through a well-known ion implantation technology, thereby controlling a threshold voltage of a memory cell transistor. Then, a gate oxide film 2 is formed on a surface of the substrate 1 with a thermal oxidation method.
As shown in FIGS. 1(b) and 1(e), in the next step, a poly-silicon film 3 as a first layer constituting a floating gate is formed on an entire surface of the structure with a well-known CVD (Chemical Vapor Deposition) method. The, an impurity such as phosphorous is implanted into the poly-silicon film 3 for reducing an electrical resistivity of the floating gate.
In the next step, a resist pattern is formed on the poly-silicon film 3 through a well-known photolithography technology. The resist pattern has opening portions extending along centerlines of the element separation regions 20 and having a width slightly larger than a channel width of the memory cell transistor. Then, the poly-silicon film 3 is etched through a well-known dry etching technology with the resist as a mask, thereby forming slit portions 3a along the centerlines of the element separation regions 20.
As shown in FIG. 1(c), in the next step, an interlayer insulation film 4 is formed on the entire surface of the structure with the well-known CVD method. Then, a poly-silicon film 5 as a second layer constituting a control gate is formed on the interlayer insulation film 4 with the well-known CVD method. Then, a composite film 6 formed of materials such as tungsten (W) and silicon (Si) is formed on the poly-silicon film 5 for reducing a wiring resistivity of the control gate with the well-known CVD method.
As shown in FIGS. 2(a) and 2(d), in the next step, a resist pattern is formed on the structure through the well-known photolithography technology. The resist pattern has opening portions corresponding to a pattern of a laminated gate. Then, the composite film 6, the poly-silicon film 5, the interlayer insulation film 4, and the poly-silicon film 3 are sequentially etched in a depth direction through the well-known dry etching technology with the resist as a mask, thereby forming laminated gates 21.
Through the steps described above, when a plurality of the layers is concurrently etched using the single mask, the poly-silicon film 5 and the poly-silicon film 3 become the control gates 5 and the floating gates 3 in a self-compatible manner along a channel length direction.
In the step described above, a portion of the floating gate 3 corresponding to the slit portion 3a has a thickness smaller than that of other portion of the floating gate 3. Accordingly, in the process of the etching, a surface of the substrate 1 under the slit portions 3a is etched, thereby forming trenches 7 in the substrate 1 along the slit portions 3a. 
As shown in FIG. 2(b), in the next step, a silicon oxide (SiO2) film (not shown) is formed on the entire surface of the structure with the well-known CVD method as a protective layer during a process of ion implantation.
In the next step, an impurity of an n-type such as phosphorous is implanted with the laminated gates 21 thus patterned as a mask with the well-known ion implantation method. Accordingly, drain/source regions 8 containing a high concentration n-type impurity are formed in the surface of the substrate 1 exposed on both sides of the laminated gates 21 and bottom surfaces of the trenches 7.
As shown in FIGS. 2(f) and 2(e), in the next step, an interlayer insulation film 9 is formed on the entire surface of the structure with the well-known CVD method. Then, contact holes 10 are formed in the interlayer insulation film 9 up to the surface of the substrate 1 through the well-known photolithography technology and the well-known dry etching technology.
As shown in FIG. 2(e), the contact hole 10 is formed between the element separation regions 20 over the trench 7, and extends to the drain/source regions 8 facing with each other with the trench 7 in between. Then, a conductive material is filled in the contact holes 10 to form a wiring portion (not shown), thereby completing the conventional non-volatile semiconductor memory. (Refer to Patent Reference 1, Patent Reference 2, and Patent Reference 3)
Patent Reference 1: Japanese Patent Publication No. 03-126266
Patent Reference 2: Japanese Patent Publication No. 03-52267
Patent Reference 3: Japanese Patent Publication No. 2004-55657
In the conventional non-volatile semiconductor memory described above, the trenches 7 have a relatively large width. When the contact holes 10 formed in the interlayer insulation film 9 have a small diameter, or the contact holes 10 are formed at positions shifted relative to the trenches 7 due to a shift in alignment of the mask, it is difficult to sufficiently expose an upper surface of the drain/source region 8 in the contact hole 10. Accordingly, the wiring portion filled in the contact hole 10 may not sufficiently contact with the source/drain region 8, thereby increasing a contact resistivity and deteriorating performance of the conventional non-volatile semiconductor memory.
To this end, it has been tried to reduce a width of the trenches 7 through improving a mask or optimizing a condition of the photolithography. However, it is difficult to reduce a width of the trenches 7 only through optimizing a condition of the photolithography, and to completely solve the problems of the conventional non-volatile semiconductor memory.
In view of the problems described above, an object of the present invention is to provide a method of producing a non-volatile semiconductor memory capable of solving the problems of the conventional semiconductor memory. In the method of the present invention, it is possible to stably produce the non-volatile semiconductor memory having a laminated gate structure at a high yield.
Further objects and advantages of the invention will be apparent from the following description of the invention.